In broadband communication systems, moving data between processors, memory locations, and ports is one of the most critical tasks. Typically, a modem receiver transfers data from a receiving FIFO to memory storage, coprocessors, such as a cyclic redundancy check (CRC) checker, and bit-alignment circuits. The data may be further transferred to a host processor, backplane interface or other destination. In the case of a modem transmitter section, the data is transferred among the same components in the reverse direction. The data-moving function is one of the biggest users of the CPU in high-speed modems.
FIG. 1 illustrates a typical distribution of CPU cycles 100 for a modem providing the High-Speed Downlink Packet Access (HSDPA) communications protocol. Chart 100 illustrates relative amounts of processing time required for each of the functions in list 101. As shown in the FIG. 1, the data-handling functions, such as data copy 102, data storage 103, and memory allocation 104 operations account for almost three-quarters of the CPU cycles. On the other hand, radio link control (RLC) packet data unit (PDU) allocation 105, RLC header decoding 106, and other 107 data-processing operations account for only about one-quarter of the CPU cycles.
To increase data-transfer rates, data-moving functions have been implemented in prior hard-wired circuits. For example, dedicated data-move accelerators may be used in VDSL and HSDPA chips. These accelerators are specialized for specific tasks—i.e. VDSL or HSDPA applications—and have limited configurability. As a result, known data-move accelerators cannot be reused with other protocols or in other contexts. A significant amount of time and effort are required for the design and verification of the hardwired data-move accelerator blocks in each generation of the chips. Additionally, further evolution (i.e. later versions) of protocol standards are difficult or impossible to implement in an existing data-move chip after it has been designed.
The standard solution for data transfer is a direct memory access (DMA) Controller, which is well-known for use in moving data between a CPU, memory and peripherals. The basic function of a DMA controller is to move a sequence of data from a source address to a destination address. The host CPU normally configures the DMA control registers with relevant parameters, such as source address, destination address, and number of words to transfer, and retrieves execution states from the status registers.
More advanced DMAs, such as the ARM PrimeCell DMA Controller (PL080), may work through a linked list of descriptors with a predefined list structure. These DMA controllers set status registers to indicate IDLE, RUN, and ERROR states and send interrupts to the host processor upon termination or error conditions. Generally, a DMA controller provides simple acceleration functions and relies on the intelligence of the host controller. The host CPU is frequently interrupted for high bandwidth data transfers, which significantly degrades the performance of the CPU for other tasks. Even if the host processor has the ability to hide interrupt latency, using multithreading, for example, the configuration parameters have to be updated frequently, such as for each data frame, which causes further performance degradation of the host CPU.